As integrated circuits become increasingly laden with metal or polysilicon interconnects, the resulting interconnect capacitances are rapidly becoming a bottleneck in the design of faster ICs. It has therefore become very important to model these capacitances in order to accurately simulate the performance of ICs. However, it is difficult to make measurements of modeled interconnect capacitances with high accuracy and resolution. As a result, the extraction of interconnect parameters using these measurements is often not precise. This causes circuit simulations performed without correctly extracted interconnect parameters to be inaccurate and unreliable.
In the past, on-chip test structures have been used in attempts to model interconnect capacitances with higher accuracy and resolution. However, many of these test structures suffer from significant deficiencies which make them inefficient and/or result in interconnect capacitance measurements made with them being inaccurate and/or having low resolution.
For example, the on-chip test structures disclosed in Khalkhal, A., et al., On-Chip Measurement of Interconnect Capacitances in a CMOS Process, Proc. IEEE 1995 Int. Conf. on Microelectronic Test Structures, vol. 8 (March 1995), Gaston, G. J., et al., Efficient Extraction of Metal Parasitic Capacitances, Proc. IEEE 1995 Int. Conf. on Microelectronic Test Structures, vol. 8 (March 1995), Shyu, J. B., et al., Random Effects in Matched MOS Capacitors and Current Sources, IEEE Journal of Solid State Circuits, vol. sc-19(6):948-955 (December 1984), Kortekaas, C., On-Chip Quasi-Static Floating-Gate Capacitance Measurement Method, Proc. IEEE 1990 Int. Conf. on Microelectronic Test Structures, vol. 3 (March 1990), and Laquai, B., et al., A New Method and Test Structure for Easy Determination of Femto-Farad On-Chip Capacitances in a MOS Process, Proc. IEEE 1992 Int. Conf. on Microelectronic Test Structures, vol. 5:62-66 (March 1992), require a reference capacitor and/or a complicated test structure design and measurement set-up. Moreover, these test structures provide only picofarad or femptofarad resolution and occupy a large chip area.
An improved test structure with attofared resolution is disclosed in Chen, J. C., et al., An On-Chip, Attofared Interconnect Charge-Based Capacitance Measurement (CBCM) Technique, Proc. of IEDM 1996, pp. 69-72. This test structure has a reference structure and a target structure. The reference structure is identical to the target structure except that the interconnect configuration of the reference structure does not include the target interconnect capacitance to be modeled and measured. The difference in current between charging (or discharging) the total capacitances of the reference and target structures is then used to compute a measurement of the target interconnect capacitance.
One problem with such a test structure is that it requires a corresponding reference structure for the target structure. This obviously increases the chip area of the entire test structure.
Another problem is that the test structure can only be used to measure one target interconnect capacitance. Thus, if an IC designed by an IC designer has a complicated interconnect configuration with many interconnect capacitances in close proximity to each other, a separate test structure is required for each of these interconnect capacitances. This increases the chip area of the IC chip on which all of the test structures are formed.
Conversely, if only one test structure is used for a complicated interconnect configuration, only one lumped interconnect capacitance can be modeled and measured. This means that the specific interconnect capacitances that comprise the lumped capacitance cannot be separately modeled and measured.
In view of the foregoing, it would be highly desirable to provide an improved test structure that has small chip area and is capable of separately modeling all of the specific interconnect capacitances in a complicated interconnect configuration. Ideally, the interconnect capacitance measurements made with such a test structure could be used to extract interconnect parameters for accurately simulating ICs.